1. Field of the Invention
The present invention relates to the field of fabrication of interconnections in integrated circuits, particularly to a solder bump structure used to provide electrical contact between a semiconductor chip and the environment, and it also relates to a method of forming a solder bump structure.
2. Description of the Related Art
The need for high-performance semiconductor chips has continually increased over the past several years, while at the same time the functionality of the circuitry has become more complex and the amount of area per chip has decreased. In general, an increase in functionality requires the provision of a large number of single electronic devices that need to be electrically interconnected to form a plurality of functional units. In order to output signals to, and receive signals from, an external source, an appropriate interface between the chip and the external source is necessary which provides the input/output (I/O) capability required. Modern integrated circuits (ICs), such as CPUs, must therefore include a large number of contact pads or bond pads on the chip to establish an electrical connection to peripheral devices via an appropriately formed chip package. Thus, one major aspect in fabricating ICs is the formation of efficient and reliable interconnections, both electrically and mechanically, between the contact pads and the package.
One technique widely used for making interconnections between the chip and the package is wire bonding. According to this bonding technique, flexible wires are attached one at a time from the bond pads on top of the chips to the leads of the package. The materials used for wire bonding are typically gold or aluminum since these materials are highly conductive and adhere well to the metallization formed on both the chip and the package.
The employment of flexible wires, however, imposes certain constraints on the applicability of wire bonding. One of these limitations resides in the fact that the length of a single wire is restricted from about 1-4 mm to minimize the risk for shorts at adjacent wires, as longer wires are likely to droop or to be deformed. Thus, the location of the bond pads is substantially restricted to the chip perimeter. Consequently, a high I/O capability requires a large chip area, which renders wire bonding a less attractive bonding technique for modem, highly complex ICs. A further drawback of wire bonding is that even after a wire bond is formed on the aluminum bond pad, a fairly large area of the pad remains exposed and allows any material to react with the aluminum, as aluminum is a chemically reactive material which readily reacts even with pure water.
According to another bonding technique, referred to as tape automated bonding (TAB), bond bumps are formed at the periphery of the chip and are then bonded to a wiring arrangement formed on a flexible tape. The wiring pattern formed in the tape replaces the flexible wires used in wire bonding and thus eliminates some of the drawbacks of wire bonding.
According to a further technique, i.e., the so-called flip chip technology, solder bumps are formed on contact pads provided at respective locations across the entire chip surface. After reflowing the solder bumps to create solder balls, these solder balls are brought into contact with and aligned to a package, a print board, and the like, which comprise a pad arrangement that is a mirror image of the chip pad arrangement. Subsequently, the chip and package are attached to each other by reflowing the solder balls so as to establish an electrically and mechanically reliable connection.
With reference to FIGS. 1a-1f, a typical prior art process for forming solder bumps according to the flip chip technology will be briefly described. FIGS. 1a-1f show schematic cross-sectional views of a semiconductor structure at various manufacturing stages representative for the formation of solder bumps.
As shown in FIG. 1a, a substrate 1, such as a silicon substrate or any other substrate appropriate for semiconductor or IC technology, is provided and may include various layers and structures defining active and passive semiconductor regions. Leads (not shown) in the form of doped areas or buried layers in the substrate 1 are connected to a contact pad 4 substantially consisting of aluminum and formed in a passivation layer including a silicon dioxide layer 2 and a polyimide layer 3. The passivation layer 2, 3 covers the edges of the contact pad 4. Patterning of the passivation layer 2, 3 is performed by lithographical techniques that are well known in the art.
As shown in FIG. 1b, a multilayer metal film 5, for example including a titanium/tungsten (TiW) layer, a chromium/copper (Cr/Cu) layer and a copper layer, is formed on the passivation layer 2, 3 and the contact pad 4 by, for instance, sputter deposition.
As depicted in FIG. 1c, in a further advanced manufacturing stage, the substrate 1 further comprises a photoresist mask 6 having an opening 7 above the contact pad 4.
Referring to FIG. 1d, in a next manufacturing stage, the substrate 1 comprises a solder bump 8 including, for example, lead (Pb) and tin (Sn) that is formed in the opening 7.
According to a typical prior art process, the structure depicted in FIG. 1d may be formed in conformity with the following process flow. After patterning the photoresist mask 6, the substrate 1 is inserted in a plating bath including lead (Pb) and tin (Sn) containing sulfates. The edge region of the substrate 1 is connected to one of two electrodes, whereas the other electrode is located in the bath in the vicinity of the substrate 1. After applying a voltage across the electrodes, e.g., a DC voltage or a pulsed DC voltage, a current flow is generated from the substrate perimeter to the opening 7 via the multilayer metal film 5, thereby reducing lead (Pb) and tin (Sn) ions which are then deposited at the bottom of the opening 7 to gradually form the solder bump 8. To create a large number of solder bumps 8 exhibiting a satisfactorily identical structure, the multilayer metal film 5, acting as a current distribution layer, needs to be uniformly deposited on the substrate 1 to supply substantially the same amount of current to each opening 7.
FIG. 1e shows the substrate 1 with the photoresist mask 6 removed.
FIG. 1f shows the substrate 1 in a further advanced manufacturing stage, wherein the multilayer metal film 5 is partially removed to electrically insulate the solder bump 8 from the remaining substrate surface. The multilayer metal film 5 may be removed by etching each of the layers constituting the multilayer metal film 5, wherein the solder bump 8 serves as an etch mask for that portion of the multilayer metal film 5 that is located below the solder bump 8. This portion, also sometimes referred to as under-bump metallization, serves as an adhesion layer and a diffusion barrier to avoid diffusion of the lead (Pb) and tin (Sn) atoms into the underlying layers while ensuring a sufficient mechanical adhesion of the solder bump 8 to the remaining contact pad 4. During this etch process, the solder bump 8 may be underetched up to approximately 10 xcexcm depending on the type of etch process, the dimensions of the solder bump 8, and the thickness of the individual sublayers of the metal film 5. As a consequence, edge regions 10 and 11 of the contact pad 4 may be exposed and oxidized, resulting in a deteriorated performance of the completed bond contact. Furthermore, since the removal of the multilayer metal film 5 requires a highly complex etch process, such an underetch depends on a variety of parameters that are mostly undefined, so that the area covered by the multilayer metal film 5 may vary in accordance with unavoidable variations of the parameters. Therefore, the size of a solder ball formed by reflowing the solder bump 8 may also vary since the solder of the bump 8 usually recedes onto the metal film 5, i.e., the under-bump metallization, during reflowing the solder due to surface tension of the liquid solder material.
Especially in applications necessitating a large number of interconnects, it is extremely important to provide substantially equally formed solder balls, and thus solder bumps, to ensure a reliable connection of each individual solder ball with its respective counterpart on the package, as already the failure of a single solder bond may lead to a complete failure of the entire IC.
Accordingly, the present invention is directed to a bump structure and a method allowing the fabrication of bumps with well-defined dimensions.
According to one embodiment of the present invention, a method of forming a solder bump comprises providing a substrate having formed thereon a contact pad and a passivation layer covering the perimeter of the contact pad. Moreover, a first metal film is deposited on the substrate and a second metal film is deposited on the first metal film. Additionally, the second metal film is patterned to form an opening, wherein the opening isolates an inner region of the second metal film from an outer region of the second metal film, whereby the inner region covers the contact pad. Furthermore, the method comprises depositing a metal in the inner region and in the opening.
According to a another embodiment of the present invention, a solder bump structure comprises a substrate having formed thereon a contact pad formed in a passivation layer, a first metal film formed on the substrate and the contact pad, and a second metal film formed on the first metal film, wherein the second metal film has an inner region above the contact pad and an outer region separated from the inner region by an opening formed in the second metal film around the contact pad. The solder bump structure further comprises a solder formed on the inner region of the second metal film and at least partially formed in the opening.